1. Field of the Invention
The present invention relates to a circuit structure of a memory cell and a memory, more particularly to a device and a method for breaking leakage current path within a memory cell and a memory device.
2. Description of the Related Art
Traditionally, a semiconductor memory device includes a non-volatile memory and a volatile random access memory (RAM). The non-volatile memory retains the stored data even the power applied thereto is turned off, while the volatile memory, such as a static random access memory (SRAM) and dynamic a random access memory (DRAM), loses the stored data when the power applied thereto is turned off.
As to the volatile memory, the difference between SRAM and DRAM is that the storage unit of SRAM is transistors. Therefore, SRAM has a speed five times of that of DRAM. However, the cell size and cost of SRAM are higher than those of DRAM. Therefore, DRAM is a more popular memory because of its smaller cell size and low cost. Because DRAM uses capacitors for storing data, charges stored deplete gradually because of the leakage current therefrom. Therefore, a periodic refresh is required. Once the power applied thereto is turned off, the stored data will be lost. Even if a power is applied thereto, the stored data is gradually lost and a refresh step is required because of leakage current generated therefrom.
Basically, a memory cell of a DRAM is composed of a transistor and a capacitor. Please referring to FIG. 1, FIG. 1 shows a schematic drawing of a unit cell structure of a DRAM, wherein the logic state of a DRAM depends on whether charges are being stored within the capacitor or not. When the density level of a DRAM is high and the cell size of a DRAM becomes small, it is hard to avoid circuit short resulting from process defects. Please referring FIG. 1, a traditional DRAM array, for example, includes memory cells 102 and 104, as well as a sensing amplifier 106, wherein a defect generated during manufacturing results in a short of the bit-line and word-line of the memory cell 102 at A. Therefore, a leakage current F from a power supply terminal VBLEQ flows through the bit-line to the ground terminal of the capacitor within the memory cell 102. When the memory is in a stand-by state, the leakage current consumes a substantial amount of the power. The longer the stand-by state, the more the power is consumed.
Generally, in order to maintain a high signal to noise (S/N) ratio, it is impossible to reduce the capacitance for reducing the leakage current. The leakage current usually is about 300 μA at each short spot. A prior art method for improvement is disclosed. FIG. 2 is a circuit structure of an improved DRAM cell. As shown in FIG. 2, a current-limit device, such as a depletion mode NMOS transistor 212 having a low threshold voltage, is connected to the bit-line precharger of the memory cell 102 for reducing leakage current. By the current-limit device, the leakage current can be reduced to 15 μA at each short spot.
However, the disadvantage of the current-limit device described above is that the leakage current still exists and a longer time for precharge is required even though defective memory cells in the array of memory cells are replaced by redundancy cells. Moreover, the total leakage current is proportional to the number of the defective memory cells. As to the electronic devices, such as portable devices, for example, notebooks, the leakage current will substantially reduce the service life of batteries, slow the speed of memory devices, and increase the temperature of computers. Therefore, a device and a method for breaking the leakage current path is desirable.